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Inside this smartphone are 62 microchips
containing a total of 90 billion transistors.
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These microchips are incredibly powerful and
the cornerstone of all technology, but how are
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billions of nanoscopic transistors manufactured
into a microchip the size of a tiny ant?
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Well, all these microchips were manufactured in
a semiconductor fabrication plant like this one.
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Inside it is a clean room which spans the area of
8 football fields and is filled with hundreds of
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machines ranging in size from that of a van to
that of a city bus and costing anywhere between
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a few million and 170 million dollars. Within
this microchip factory, silicon wafers travel
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from machine to machine and undergo around a
thousand processes over a 3-month period. And,
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by the end of production, each silicon wafer
will be covered in hundreds of CPU chips
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each containing 26 billion transistors.
When we zoom in we can see the nanoscopic
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transistors at the bottom and over
a dozen layers of wires above. This
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integrated circuit is then cut out from
the wafer, tested, and packaged so that
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it can be installed into your desktop computer.
In this video we’re going to explore the entire
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microchip manufacturing process and show
you how billions of nanoscopic transistors
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and an impossibly complex 3D maze of wires
are manufactured in one of the world’s most
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technologically advanced microchip factories.
It’s an incredibly complicated process,
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so stick around and let’s jump right in! A portion
of this video is sponsored by Brilliant.org.
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There are two sides to understanding how microchip
manufacturing works. The first is the sequence of
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steps and processes needed to build the nanoscopic
transistors and the labyrinth of wires. Whereas
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the second is how the semiconductor fab and
multimillion dollar equipment on the cleanroom
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floor work, and we’ll be flipping between
these two sides to get a complete picture.
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Let’s start by opening up this desktop computer,
focusing on the CPU and taking a look at what’s
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inside. Here we have an integrated circuit, or
die, which we’ll refer to as a chip. This chip
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has 24 cores, a memory controller, a graphics
processor, and many other sections. Within one
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of the cores, we can see its block diagram
and the various elements. Zooming in on
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this multiply block, we find a layout of 44
thousand transistors that physically execute
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32-bit multiplication and constitute just
point zero zero zero one seven percent of the
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overall 26 billion transistors in the CPU.
Zooming in even further, we see layers of
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metal wires, or interconnects, and at the very
bottom are the transistors that form the basic
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logic gates. Note that these layers of metal
interconnects aren’t floating, but rather,
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the empty space that you see is filled with
insulating materials, thus providing structure,
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and preventing the metal wire layers from
touching. Furthermore, here we’re only showing
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the transistors at the bottom and five layers of
metal interconnects with vias traveling vertically
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between the layers. In actuality there are a
total of 17 metal layers of wires in the CPU,
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and each successive set of levels uses larger
and larger interconnects. At the bottom are
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local interconnects that move data around this
32 bit multiply circuit. In the middle are
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intermediate interconnects that move data around
the core, and at the top are global interconnects
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that move data around the entire CPU.
You might be wondering how small are
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these transistors? Zooming in again and past
the interconnect layers we find FinFets,
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which are transistors whose channel dimensions
are 36 by 6 by 52 nanometers with a transistor
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to transistor pitch of 57 nanometers. Clearly
the transistors are incredibly small. Here’s
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a mitochondria, a dust particle, and
a human hair for size comparisons.
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Now that you have a sense of what the transistors
and labyrinth of metal interconnects look like,
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let’s explore how they’re manufactured.
We’ll begin with an analogy. Imagine baking
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a cake that’s 80 layers tall, with each layer cut
to a unique shape. To make this cake there are
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940 steps in the recipe, which takes 3 months
to complete and includes hundreds of exotic
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ingredients. And, if any measurement, baking
time, or temperature is more than one percent off,
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then the cake is entirely ruined. That’s
kind of what it’s like to make a microchip,
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but microchips are even more complicated.
Let’s look at a single layer of this integrated
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circuit and run through a simplified
set of steps used to build it. To start,
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a layer of insulating silicon dioxide is deposited
on top of the wafer and then a layer of light
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sensitive photoresist is spread across the top.
Next, using UV Light and a stencil, a pattern is
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applied to the photoresist. Solvents then are
used to remove the areas hit by the UV light,
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thus creating a patterned mask layer. Using the
mask, the revealed silicon dioxide is etched away
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down to the previous layer. Next the mask layer is
removed, and a layer of copper is added to cover
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the wafer and fill in the areas that were just
etched away. Finally, the surface is ground down
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and leveled off to reveal the copper and insulator
patterns. And thus, a single layer is completed.
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In order to build the next layer, which is
a vertical set of metal vias, we repeat the
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same set of steps, but use a different pattern
for the photomask. Since these layers are all
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built using the same set of steps it’s more
effective to visualize the steps as a circle
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like a clock. To build all the 80 layers of the
die, this sequence is repeated over and over,
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resulting in 940 steps. One important note is
that the FinFet transistors at the bottom are
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even more complicated than the metal wires, and
thus additional steps are needed to fabricate
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them. Furthermore, cleaning the wafer to wash away
dust particles that may have landed on the wafer,
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as well as inspecting the wafer to make
sure everything is being built properly,
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happens frequently and these steps need to
be added to the circle. A different tool is
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used to complete each of these process steps. .
Now that we have an understanding of the steps,
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let’s take a look at this semiconductor
fabrication plant. This CPU is manufactured
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on a 300-millimeter silicon wafer which can
fit 230 CPU chips. In contrast DRAM chips are
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considerably smaller and thus 952 of them can fit
on a wafer. These silicon wafers are carried in
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stacks of 25 using a container called a front
opening universal pod, or foup. This sealed
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plastic wafer carrier is transported around the
cleanroom floor using an overhead transport system
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which lowers the foup onto the tool’s landing pad.
Inside the tool, robotic arms transport the wafer
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through vacuum load locks and to different
process chambers where materials are added,
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removed, or processed in ways that we’ll explore
later. The wafers are then returned to the foup,
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resealed inside, lifted up to the overhead
transport system, and carried to and dropped
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onto the next tool, where the next step in the
process is completed. To build the entire chip
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composed of 80 different layers it takes 3 months
of traveling from tool to tool where at each
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stop one of the 940 process steps is completed.
In order to increase the microchip mass production
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capabilities of a semiconductor fabrication
plant or fab, typically there are dozens of the
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same semiconductor tools organized in rows that
perform the same process. On the cleanroom floor
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there are a total of 435 semiconductor tools
resulting in the fab’s production capacity of
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50,000 wafers or 11.5 million CPUs a month.
These tools have rather complicated names,
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so we’ll start by categorizing them according
to their functionality. There are 6 groups:
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making the mask layer, adding material,
removing material, modifying the material,
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cleaning the wafer, and finally inspecting
the wafer. We’ve color coded the different
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functional groups to the various tools and
process steps to help you not get lost.
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Let’s next look at each of these semiconductor
tools and see how they process the wafer in
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various ways. We’ll start with the ones that are
used to make the mask layer or the nanoscopic
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stencil on the wafer. These tools include the
photoresist spin coater, photolithography tool,
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developer and photoresist stripper. First the
photoresist spin coater applies a light-sensitive
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layer to the surface of the wafer and sends
it through a soft bake where the wafer is
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heated in order to evaporate the solvent from
the photoresist. Next the wafer goes to the
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lithography tool which shines UV light through a
stencil, which is technically called a photomask.
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The light passes through the stencil and is then
demagnified or shrunk down to produce a nanoscopic
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pattern on the wafer. Wherever the light from
the stencil touches the wafer, the photoresist is
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weakened. The wafer then goes to the developer
and the weakened photoresist is washed away,
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leaving only the patterned nanoscopic stencil on
the wafer. The wafer is then sent through a hard
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bake to harden the remaining photoresist.
Next the wafer travels to other tools to
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undergo processing, and once these processes
are completed the wafer goes to a photoresist
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stripper which uses solvents to dissolve and
remove the photoresist mask layer. And that’s
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how a mask layer is formed and then removed.
The photolithography tool is one of the most
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important, so let’s take a look at it. Inside
is a UV light source, a set of lenses to
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focus the light, a photomask which contains the
stencil, or design of the layer to be patterned,
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and a wafer carrier. The photomask is 6 by 6
inches, and, based on the dimensions of the CPU,
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can fit 2 copies of a single layer of
the CPU design. The purpose of using
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a photomask with these crazy optics is because
it’s a reliable way to copy and paste a design
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for billions of nanoscopic transistors and wires
onto 230 identical CPUs on a single wafer in a
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few minutes. After the light passes through the
photomask, the UV light goes to more lenses in
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order to shrink down the pattern by a factor of
4 and print a single layer of the design onto the
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photoresist. The wafer carrier steps from position
to position, printing the photomask image at each
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stop, until all 230 chips are patterned.
Let’s clarify one detail. In our previous
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examples, we talked a lot about this CPU having 80
layers. Specifically, what we were referring to is
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the number of photomasks and mask layers used to
create all the different layers of patterns on
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the wafer. Therefore, one complete CPU chip
uses 80 different photomasks, each costing
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300,000 dollars. With only one mask layer being
patterned at a time, this CPU chip will undergo 80
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separate visits to the lithography tool. We could
spend another hour talking about photolithography
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but let’s move onto the next category of tools.
Deposition tools are used to add or deposit
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material onto the wafer. A lot of times we
use the mask layer from the photolithography
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step to add materials to the areas uncovered
by the mask layer, kind of like spray painting
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through a stencil. Due to the wide range of
elements and compounds used to create the layers,
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deposition tools have a wide range of variations
with complicated names and acronyms for each
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variant. But essentially there are 3 key groups
of materials that are added or deposited onto
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the wafer: metals such as copper or tantalum,
insulators which are typically called oxides,
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and crystalline layers of silicon. Each group of
different materials uses different physics and
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chemistry principles to deposit the material
on the wafer and therefore has a different
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technical name for the tool that deposits the
material. Deposition tools typically have a
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central wafer handling chamber, with the various
chambers attached to the edges, each one dedicated
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to adding just a single element or compound.
The next category of machines do the opposite,
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which is to remove material. There are 2
key methods. The first is etching. Etchers
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use either corrosive chemicals or high energy
plasmas to react with and remove materials from
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the surface of the wafer. They are typically used
with the mask layer stencil in order to remove the
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material exposed by the mask, thus creating a hole
that can be later filled by a deposition tool.
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The second method to remove material is CMP,
which is chemical mechanical planarization. CMP
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applies slurry and uses abrasive pads to grind
and polish away the top surface of the wafer,
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making it perfectly flat. CMP levels off the top
layers of the wafer and is typically used as the
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last step in a cycle of processes in order to
prepare the wafer for another layer to be added.
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The fourth category are tools that modify the
silicon and are called ion implanters. These tools
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use the photomask stencil to bombard the unmasked
regions with phosphor, boron, or other elements
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in order to make the P and the N regions required
to form the transistors themselves. Therefore, ion
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implanters are only used in the front end of line.
You might think that this is adding material.
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However, ion implanters only add around one atom
of phosphor or boron for every 10,000 atoms of
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silicon. Additionally, while other machines spray
paint a layer on top of the wafer, ion implanters
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hurl atoms deep into the silicon lattice, kind
of like a cannon launching a baseball 6 feet into
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a concrete wall. This process typically damages
the silicon lattice, which is why the following
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step is to repair the silicon by heating the
wafer using a separate tool called an annealer.
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The fifth category of tools are used to clean
and remove any contaminants or particles from the
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wafer. These wafer washers use ultra-pure water to
clean the wafer and then dry it with nitrogen or
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hot isopropyl alcohol. Cleaning the wafer happens
rather frequently in order to remove any stray
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particles that may have fallen onto the wafer.
And finally, sixth are tools that inspect the
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transistors and metal layers for defects and
are called metrology tools. A common metrology
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tool uses a scanning electron microscope with
nanometer-level resolution to take pictures of the
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top surface of the wafer and determine if there
are defects such as improperly patterned layers
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or particles on the surface. When fabricating
an integrated circuit that takes 3 months to
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complete, it’s important to repeatedly monitor the
progress and make sure that each of the processes
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is being executed with nanometer-level precision.
Now that we’ve covered each of the categories,
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here are the color coded process steps
along with the layout of the tools in the
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semiconductor fabrication plant. Let’s run
through the complete set of steps used to
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manufacture a single metal interconnect layer.
First a layer of insulating silicon dioxide is
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deposited onto the wafer. Next photoresist is
spread across the surface and the wafer is sent
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through a soft bake to remove the solvent. The
wafer then travels to the photolithography tool
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where the design from the photomask is transferred
to each of the chips on the wafer by weakening
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the areas of photoresist hit by the light. The
wafer next goes to the developer to wash away
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the sections that were hit by the light from the
lithography tool and then through a hard bake to
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harden the remaining photoresist. With the mask
layer built, the wafer goes to an etching tool,
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where a plasma etcher removes a vertical column
through the exposed silicon dioxide until it
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reaches the previous layer’s metal vias. Next the
wafer is sent to a photoresist stripper where the
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mask layer is removed. The wafer then travels
to a physical vapor deposition tool where a
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sequence of metals fills in the exposed pattern
and coats the wafer in metal. Finally the wafer
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is sent to a chemical mechanical planarization
tool where the metal is ground down so that all
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that remains is a flat layer of insulating silicon
dioxide and conductive copper interconnects that
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match the pattern from the photomask. A single
metal layer is now completed, and the wafer is
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ready for the next cycle to begin where insulating
silicon dioxide and the vias will be added. Note
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that cleaning and wafer metrology or inspection
steps occur in between many of these other
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steps. Furthermore, the process steps to make the
transistors are less straightforward and utilize
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the ion implanter, and thus we’ll cover them in a
separate video on transistor physics and design.
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These steps are for building the
integrated circuit on the wafer, however,
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there are additional steps in manufacturing a
microchip which we’ll explore in a little bit.
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But before we get there, one important thing
to note is that the semiconductor industry
00:20:32
is incredibly secretive regarding the exact tool
layout and the process steps and recipes used to
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make the transistors. We wanted to make the best
video on how microchips are made and it took us
00:20:47
180 hours of scouring the internet and textbooks
for information and reference images and, using
00:20:55
what we found, we spent 205 hours modeling each
of these tools, the many layers of the integrated
00:21:03
circuit, and the semiconductor fab. Furthermore,
writing the script took about 100 hours, and then
00:21:12
animating all these visuals took more than 825
hours. As a result, this video took over 1300
00:21:22
hours to make, and it’s entirely free to watch.
We want to make more videos like this one where we
00:21:29
explore computer architecture and how transistors
work, and we can’t do it without your help. The
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best way you can help is by taking a few seconds
to scroll down, write a comment below, like this
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video, subscribe if you haven’t already and then
share this video on social media or send it to a
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friend or colleague. Truly, just a few seconds
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Additionally, we have a Patreon page where
we’ll be releasing behind the scenes footage
00:22:05
of our work and updates for upcoming
videos. If you find what we do useful,
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we would appreciate any support. Thank you.
So then, what are the additional steps in
00:22:18
manufacturing a microchip? Before
chip manufacturing at the fab,
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we first have to manufacture the silicon
wafers by refining quartzite into pure silicon,
00:22:29
and then growing a monocrystalline ingot
and cutting it into wafers. For reference,
00:22:35
these 300-millimeter wafers are around
three-quarters of a millimeter thick,
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they have a barcode on the side and a small
notch in them to indicate the direction of the
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crystal lattice. Furthermore, these wafers are
incredibly delicate, and shatter into hundreds
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of shards when broken. A single wafer costs
around a hundred dollars, but after being
00:22:59
populated with CPUs it’s worth closer to a hundred
thousand dollars, making it quite literally ten
00:23:07
times more valuable than its weight in gold.
Moving onto the steps after chip manufacturing.
00:23:13
The completed wafer is sent to a separate building
where each of the CPUs undergoes rigorous testing
00:23:19
to figure out if it works as intended. If a CPU
works, that’s great. But frequently a particle
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or photomask defect has damaged a section of
the integrated circuit, rendering that section
00:23:33
defective. These semi-functional circuits are then
categorized, or binned, based on what still works.
00:23:40
These Intel Thirteenth Gen processors are sold as
an i9, i7, i5, or i3, depending on how many cores
00:23:50
are functional with different product lines of
CPUs whose on-board integrated graphics sections
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are defective. These wafers are transported
to another building where the chips are cut
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out using a laser, flipped over, and placed on an
interposer which distributes the connection points
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to a printed circuit board while a protective
heat conductive cover is placed on the back
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side. The printed circuit board holds the landing
grid array that interfaces with the motherboard
00:24:20
as well as various electrical components. Next
an integrated heat spreader is mounted on top,
00:24:28
and the entire assembly is tested one last time
before being packaged for sale. Finally, the CPU
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is now ready to be mounted onto the motherboard
and installed into your desktop computer.
00:24:42
It’s important to understand that chip
manufacturing requires an incredible
00:24:47
amount of science and engineering and there’s a
free and easy way to learn the basic principles
00:24:54
inside each of these complex tools and that’s with
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