00:00:00
biggest mistake I did and what most of
00:00:02
the students I see around are doing is
00:00:04
studying anything and everything that is
00:00:06
being shared on LinkedIn post YouTube
00:00:08
videos which have a title vlsi or
00:00:10
semiconductor on it things postco and
00:00:13
post AI have totally changed that is
00:00:15
from 2024 2025 hiring has become totally
00:00:19
different so your approach also has to
00:00:21
change that's why let's divide this
00:00:23
video into three parts in the first part
00:00:25
we'll see how the hiring has changed and
00:00:27
what different approach you should take
00:00:29
and then we'll see the topics you should
00:00:31
definitely Master no matter the domain
00:00:33
you want to get in and the best
00:00:34
resources topic wise these topics will
00:00:37
get you a very strong foundation and
00:00:39
then we'll see the things to study
00:00:41
domain wise like what to study for RTL
00:00:43
design verification physical design and
00:00:45
DF and then finally we'll see the
00:00:47
projects you can make domain wise using
00:00:49
open source tools the smartest way is to
00:00:52
prepare is first find what to exactly
00:00:54
study and give your 101% to master it
00:00:57
instead of studying everything out there
00:00:59
and mastering nothing if you're
00:01:01
expecting that I'll suggest too many
00:01:02
topics resources or books then you can
00:01:05
very well skip this video I believe in
00:01:07
having one best resource per topic and
00:01:09
mastering it personally I had a very
00:01:11
hard time finding what to exactly study
00:01:14
and what not to once I had filtered that
00:01:16
out 50% of my job was done I mastered
00:01:19
them and got my dream job this video is
00:01:21
mainly because I don't want you to waste
00:01:23
your time in figuring out what to
00:01:25
exactly study and the best resources for
00:01:27
them only if you're a serious student
00:01:29
watch every part of this video no matter
00:01:31
the domain you preparing for also make
00:01:34
sure to subscribe so that we can make a
00:01:36
very strong Electronics community so
00:01:37
coming to how has the hiring changed
00:01:39
postco and what you should do different
00:01:41
2024 onwards see before it was in
00:01:44
general hiring like say a company
00:01:45
required 100 entry-level employees so
00:01:48
freshers so the company usually had a
00:01:50
general hiring team manager senior
00:01:52
employees from any team like BV PD DFT
00:01:55
could be part of this hiring team this
00:01:57
hiring team usually was never role
00:01:59
specific they usually filtered out
00:02:00
students assessing them on Basics or
00:02:02
general topics like digital analog SPS
00:02:05
seos Etc say this team finally selected
00:02:08
100 students these selected 100 students
00:02:10
were then randomly sent to any team
00:02:12
whichever had openings be it RTL design
00:02:14
verification PD but now the things have
00:02:17
changed whichever team has an opening
00:02:19
that team directly goes for hiring like
00:02:22
say there is an opening in the DVT this
00:02:24
TV team only will go for hiring though
00:02:26
they might start the interview rounds
00:02:28
with General blsa topics they will most
00:02:30
likely get into the verification topics
00:02:32
like system very log or UVM they will
00:02:34
basically assess if the candidate can be
00:02:36
fit for a verification role the bottom
00:02:38
line is earlier you could be put into
00:02:40
any domain wherever the vacancy was
00:02:42
there but now you will most likely be
00:02:44
interviewed for a particular role or a
00:02:46
domain and you will get into that very
00:02:47
DET so how should your preparation
00:02:49
approach change before just studying
00:02:51
General topics was enough but now you
00:02:53
should start with your Basics and
00:02:55
prepare properly for a particular domain
00:02:57
whichever interests you but before you
00:02:58
start studying for any any domain some
00:03:00
common topics are a must to master so
00:03:02
what are the topics to start and that
00:03:04
can help you build a strong Foundation
00:03:06
you have to promise me that first you'll
00:03:08
Master these topics and only then will
00:03:10
you start doing domain specific subjects
00:03:13
these topics are very important to build
00:03:14
your base and have a strong foundation
00:03:17
so let's see these topics and the best
00:03:19
resources to cover them first Digital
00:03:22
Electronics this is your base in today's
00:03:24
world most of the electronic devices
00:03:26
have at least 80% digital circuit so no
00:03:29
matter what domain you want to get in
00:03:31
mastering digital is very important so
00:03:33
from where to study this from miso
00:03:35
Academy Digital Electronics these
00:03:37
lectures are very good to make a strong
00:03:39
Basics but practicing is is even more
00:03:42
important practice as much as you can
00:03:44
for digital I'll share two PDFs one for
00:03:47
important topics and one practice PDF
00:03:49
from which 80 to 90% questions are asked
00:03:52
in most of the semiconductor companies
00:03:54
I'll add links to both these PDFs in the
00:03:56
description below also you can join the
00:03:59
Discord chip cam Community Link which
00:04:01
has all the resources domain wise even
00:04:03
though I have shared the important
00:04:04
topics make sure to study each and every
00:04:07
topic and then you can focus more on the
00:04:10
important on what I'll suggest is you
00:04:12
can study and practice in parallel like
00:04:14
study one topic understand it properly
00:04:17
and then you can practice that very
00:04:18
topic from the PDF the book you can
00:04:20
refer is alltime best Morris Mano as I
00:04:23
said before one best reference instead
00:04:25
of four to five books for one single
00:04:27
topic second once you have mastered
00:04:29
digital you can start off with
00:04:31
implementing it practically the next
00:04:33
topic is very long all the powerful CPUs
00:04:36
and gpus you see around have all being
00:04:38
designed in verilog first this is a very
00:04:41
powerful language so verog is basically
00:04:43
a hardware descriptive language so
00:04:45
whatever you write in verilog gets
00:04:46
translated to a hardware let's say a
00:04:49
case statement becomes a MOX in real
00:04:50
life you should write a very laog code
00:04:52
in a way that it can be translated or
00:04:55
mapped to a hardware equivalent that's
00:04:57
why Hardware description language so you
00:04:59
should know what each very log Code maps
00:05:01
to on a hardware and vice versa if
00:05:03
someone gives you a hardware diagram you
00:05:05
should be able to write its very log
00:05:06
equivalent code for this what you can do
00:05:09
is first learn the basic syntax like
00:05:11
coding basic modules like marks adders
00:05:14
and then once you know the syntax and
00:05:16
the construction very log take a paper
00:05:18
and make a table on one side write very
00:05:20
log construct and on the other side make
00:05:23
it equalent Hardware structure like Cas
00:05:25
maps to a m if else maps to a priority
00:05:28
encoder once you do this you can not
00:05:30
only write synthesizable codes but also
00:05:32
tell if a code is synthesizable by just
00:05:34
looking at it so what is the best source
00:05:36
to study verilog from Hardware modeling
00:05:39
using verilog by indranil S Gupta great
00:05:42
lecture series also he has made two to
00:05:44
three videos on mapping each verilog
00:05:46
construct to its corresponding Hardware
00:05:48
so you can look into that the best book
00:05:50
I recommend for verilog would be verilog
00:05:53
HDL by Samir petar even for this I'll
00:05:56
share the PDF having important topics
00:05:58
references and digital books in the
00:06:00
description below on Discord you will
00:06:02
have it under # rtld design third the
00:06:05
next topic is seimos at the end
00:06:08
everything comes down to a transist for
00:06:10
front end roles most of the things you
00:06:12
work on are on an upper layer so yes you
00:06:14
don't need much of a transistor level
00:06:17
but still I'll suggest you to know at
00:06:19
least the basics for backend roles you
00:06:21
definitely need to study this in depth
00:06:23
but what are the basics to study working
00:06:25
of nmos BOS and then camos the main
00:06:28
topic you need to understand is camos
00:06:30
inverter characteristics for this you
00:06:32
can refer to digital IC design by
00:06:34
Professor Jan R Great Professor great
00:06:37
lectures but first watch only first 20
00:06:39
videos till seos inverter
00:06:41
characteristics and for basics of moset
00:06:43
you can watch seos digital design by
00:06:45
Professor Das Gupta from I RI my
00:06:48
favorite book for seos is digital IC
00:06:50
design by Rabbi reference YouTube links
00:06:53
and ebook for seos will be in the PDF
00:06:55
named seos which I'll add in the
00:06:56
description below and in Discord you can
00:06:59
find it under # physical design for
00:07:01
front end roles this is more than enough
00:07:03
but if you're interested in backend
00:07:05
there's definitely more to study which
00:07:06
we will discuss in the later section
00:07:09
fourth the next topic is computer
00:07:11
architecture to design any processor you
00:07:14
need this subject this subject will help
00:07:16
you understand what's exactly happening
00:07:18
in a processor how the instruction is
00:07:20
fetched decode how the operations happen
00:07:22
in a ALU how data is fetched from the
00:07:24
memory pipelining cache Concepts like
00:07:27
hit and a miss you'll get an overview of
00:07:29
of how the data and clock flows in the
00:07:31
design for computer architecture you can
00:07:33
refer miso Academy for Basics and
00:07:36
Professor SMY R for good lectures I'll
00:07:38
give the links in the description and
00:07:40
the book you can refer to now the fifth
00:07:42
topic from this topic no matter the
00:07:44
domain in both written exam and
00:07:47
interview you'll definitely get one or
00:07:49
more questions so what is this topic St
00:07:52
static timing analysis when you design
00:07:55
any circuit in real life you have to
00:07:57
take care of some things for your design
00:07:59
these are called as constraints on the
00:08:01
design and you have to meet those
00:08:03
constraints otherwise what is the point
00:08:04
of your design if the data is not
00:08:06
captured properly especially people
00:08:08
involved in design side both RTL and
00:08:10
physical design should Master this make
00:08:12
sure you don't by heart any formulas or
00:08:15
setup and hold understand exactly what
00:08:17
is setup hold data PA delay skew Jitter
00:08:21
latency uncertainty once you understand
00:08:23
directly start solving as many questions
00:08:25
as possible the same practice PDF which
00:08:28
I have shared for digital you can use
00:08:30
that to practice St as well well for
00:08:31
resources you can check out synopsis
00:08:33
guide and book you can refer to is St a
00:08:36
practical approach by jam basar and
00:08:38
Rakesh Sha but still I'll recommend not
00:08:41
to read too much theory for this just
00:08:43
the basic understanding is enough and
00:08:45
then start solving as many questions as
00:08:47
possible sixth C programming many people
00:08:50
think that coding is not required for
00:08:52
VSA companies but no you definitely need
00:08:55
to know programming as well for both
00:08:57
front end and backend you require coding
00:08:59
according to me coding is just aptitude
00:09:01
in vlsi you'll be using a lot of Eda
00:09:03
tools and to communicate with the tool
00:09:05
you obviously need to code and tell the
00:09:08
tool what needs to be done exactly so
00:09:10
the best foundation to have will be C
00:09:12
programming once you know the way the
00:09:14
data flows and how to use Loops ifls you
00:09:17
are able to code a problem statement
00:09:19
then you have got it trust me if you
00:09:21
know C you can migrate to any other
00:09:23
language easily the logic is same
00:09:25
everywhere just the syntax changes
00:09:27
especially using AI syntax won't be an
00:09:30
issue at all for C you can refer to
00:09:32
nisso Academy and practice from Geeks
00:09:33
for geeks seventh this topic is
00:09:36
understanding different flows take EIC
00:09:39
flow know the basics of what is exactly
00:09:41
happening at each stage what happens in
00:09:43
RTL design verification synthesis
00:09:45
physical design sign off I already made
00:09:48
a video on this with a very interesting
00:09:50
analogy you can watch it here eth low
00:09:53
power design techniques see when I
00:09:54
started my engineering we were at 90
00:09:56
nanometer and now we are at 3 nanometer
00:09:59
within just four to 5 years the
00:10:01
technology has shrinked so fast though
00:10:03
the chips become faster at lower nodes
00:10:05
the leakage power also increases so
00:10:07
managing power in today's day is very
00:10:10
important beat any domain you need to
00:10:12
know power management techniques so for
00:10:14
this you can refer to low power design
00:10:16
techniques by indranil S Gupta I think
00:10:18
there are around eight videos Dynamic
00:10:20
power static power leakage power very
00:10:23
important to know especially in today's
00:10:25
era nine scripting this is an add-on
00:10:28
skill but if you have have it on top of
00:10:30
your technical skill then you can be a
00:10:32
great and a powerful package but why
00:10:34
scripting so when you'll be designing a
00:10:36
chip there are a lot of metrics to take
00:10:38
care of mainly power area and speed and
00:10:41
mind you you are dealing with billions
00:10:43
of transistors here now to arrive at
00:10:46
best possible area power and speed you
00:10:48
will have to do a lot of experiments you
00:10:50
will have to compare these metrics to
00:10:52
know which experiment work out and which
00:10:54
did not there will be thousands of files
00:10:56
and it becomes very tough to analyze
00:10:58
each and every file here's where
00:11:00
scripting will help you these scripts
00:11:01
will extract the exact data you require
00:11:03
from all these files and will summarize
00:11:06
the experiments for you there are mainly
00:11:08
three top scripting languages used in
00:11:10
the industry python Pearl and tickle you
00:11:12
can choose between Pearl and python but
00:11:14
I'll recommend you to know python 10 one
00:11:17
last topic before we see what to exactly
00:11:19
study domain wise this topic is mostly
00:11:22
underestimated and neglected aptitude
00:11:24
and puzzles I'll tell you exactly what a
00:11:26
recruiter wants in you to solve any
00:11:28
problems you need two things knowledge
00:11:31
and IQ to apply that knowledge see in
00:11:33
just one hour of interview no one can
00:11:35
exactly judge your knowledge and anyways
00:11:37
they'll train you once you join them so
00:11:40
they want to see if you can solve
00:11:42
problems with basic common sense a
00:11:44
person who has a good aptitude will
00:11:46
obviously have good problem solving
00:11:47
skills if you train him well on that he
00:11:50
can be an asset to the company so at
00:11:52
least solve one puzzle daily and some
00:11:54
aptitude questions it will also sharpen
00:11:56
your brain make sure to have a timer
00:11:58
while solving in these aptitude
00:12:00
questions and keep improving your speed
00:12:02
you can solve aptitude questions from
00:12:03
India bigs or Geeks or Geeks and for
00:12:05
puzzles you can see previously asked
00:12:07
questions from Geeks for geeks one
00:12:09
advice for solving puzzles is to think
00:12:11
simple once you finish these 10 topics
00:12:14
you will have a great Foundation you can
00:12:16
check #m do on Discord where you can get
00:12:19
all these topics and resources after
00:12:21
building our foundation let's go domain
00:12:23
specific as I have told earlier being
00:12:26
domain specific is better so if you have
00:12:28
time time prepare for both front end and
00:12:30
back end otherwise choose one between
00:12:33
front end and back end and master it in
00:12:35
depth but how do you decide between
00:12:37
front end or back end if you feel you
00:12:39
have more interest or are good at very
00:12:41
LW computer architecture C then go for
00:12:43
front end but if you like CMOS SDA and
00:12:46
if you're liking this side of the flow
00:12:48
like from floor planning CTS placement
00:12:51
then go for backend but I'll not
00:12:53
recommend you to go one level down and
00:12:55
choose only design or verification so if
00:12:58
you're preparing for front content
00:12:59
prepare for both RTL design and
00:13:01
verification but before you start this
00:13:03
I'll repeat make sure you complete these
00:13:06
10 topics first which I have talked
00:13:07
about this will build a strong base and
00:13:10
only then you can start domain specific
00:13:12
topics any interview be it front end or
00:13:15
backend starts by testing your Basics if
00:13:17
you're not good the recruiter will not
00:13:19
go further say even if you're not ready
00:13:21
with the backend specific topic and you
00:13:23
are damn good with your Basics like
00:13:25
cosos SDA digital Concepts then you
00:13:28
still have a very high chance to get
00:13:29
selected but vice versa is not possible
00:13:32
it's like having a tall building with a
00:13:34
weak base the building might fall off
00:13:36
any time but with a very strong base you
00:13:38
can construct tall buildings even in the
00:13:40
future so keep this in mind before we go
00:13:43
any further now let's see domain
00:13:45
specific topics that has to be covered
00:13:47
let's start with front end in front end
00:13:48
you have majorly RTL design verification
00:13:51
and dftd the core for frontend is coding
00:13:54
for RTL design the main topics to cover
00:13:56
in proper depth are digital very log SDA
00:14:00
C programming clock domain Crossing
00:14:03
Concepts like meta stability mtbf and
00:14:06
then for scripting Pearl python once you
00:14:09
complete digital immediately install
00:14:11
Vado and start Hands-On on very L you
00:14:13
can use Eda playground also until you do
00:14:16
Hands-On and start coding you can never
00:14:18
Master very as I said earlier have a
00:14:21
table mapping all the vilog construct to
00:14:23
its corresponding Hardware now take an
00:14:25
architecture with both control and data
00:14:27
path like risky architecture and design
00:14:29
it in very log module wise make a module
00:14:32
even for the smallest part of the
00:14:34
architecture the more modules you have
00:14:36
the easier you can debug make sure to
00:14:38
write a synthesizable code and always
00:14:40
synthesize the code and check if you can
00:14:42
reduce power and area by changing your
00:14:44
RTL code sometimes a small change in the
00:14:46
style of the code can make a huge
00:14:48
difference in area and power of the
00:14:50
final circuit okay moving on once you
00:14:53
practice SDA and have a good hold over
00:14:55
it try to have constraints in your
00:14:57
design on a flop to flop path and and
00:14:59
analyze with your articl code will I be
00:15:01
able to meet the timing or I'll have to
00:15:03
change something in the code in parallel
00:15:05
keep practicing C basically even verlock
00:15:07
syntax is based on C your focus should
00:15:10
be always on writing efficient code
00:15:12
because end of the day you're a hardware
00:15:13
engineer we discuss the projects at the
00:15:16
end domain wise coming to verification
00:15:18
as the name says it's basically testing
00:15:20
the design for any bugs your core skill
00:15:23
as a verification engineer is to debug
00:15:25
the design here knowing the design is
00:15:27
also very important on that you need
00:15:29
debugging skills so to be a good
00:15:31
verification engineer you need to know
00:15:33
these Concepts in depth digital verilog
00:15:36
or system very log computer architecture
00:15:38
C and C++ specially oops Concepts UVM
00:15:42
using system very log fif synchronous
00:15:44
versus nonsynchronous fif depth
00:15:47
calculation and protocols and Pearl and
00:15:49
python for scripting learn this if you
00:15:51
have time once you have completed
00:15:54
Concepts in digital properly then move
00:15:56
on to the next topics write test benches
00:15:58
for every design you have made in very
00:16:00
long but when you write the test benches
00:16:02
think of every scenario for which the
00:16:04
design can go bad say you have four
00:16:06
inputs to a design so you need to try
00:16:09
all the two power four combinations then
00:16:11
move to system very log once you have a
00:16:13
good grip over very log most of the
00:16:15
things will be the same syntax wise just
00:16:17
a few data types here and there will be
00:16:19
different system verog is a more
00:16:21
powerful tool for verification also you
00:16:24
need to learn o op Concepts required for
00:16:26
system very log for this you can refer
00:16:28
to system system vog classes by Cadence
00:16:30
Design system available on YouTube op
00:16:33
Concepts discussed here are what exactly
00:16:35
you need to know in SV you need to
00:16:37
master task versus functions folk joint
00:16:40
statements inheritance polymorphism
00:16:43
randomization and assertions next
00:16:46
computer architecture is very important
00:16:48
subject for verification say you need to
00:16:50
verify at s so level this is like
00:16:52
verifying a processor so you need to
00:16:54
have an understanding of how the data
00:16:56
and clock flows in the architecture once
00:16:58
you understand the design only then will
00:17:00
you be able to debug it knowing
00:17:02
protocols like axi Amba and all the
00:17:05
famous protocols will be a plus that
00:17:07
will help you to understand the
00:17:09
architecture better verification
00:17:11
projects and tools we'll discuss at the
00:17:13
end all the resources for verifications
00:17:15
I'll share in the description or you can
00:17:17
get it under #d design verification on
00:17:19
Discord next coming to design for test
00:17:22
DF here the main objective is to test
00:17:25
the chip for any manufacturing def this
00:17:27
team inserts SC and change into the
00:17:29
design so that the chip can be tested
00:17:31
for any manufacturing Defence we can get
00:17:34
deep into DFT or what it exactly does in
00:17:36
some other video for now let's see what
00:17:39
to study for this of course digital then
00:17:41
CDC clock domain Crossing testability
00:17:44
generating test patterns like atbg best
00:17:47
Concepts and in practice PDF solve each
00:17:50
and every question from chapter 9 fault
00:17:52
analysis and Hazards for resources you
00:17:55
can refer to nptl indrasen Gupta
00:17:57
physical design lectures from 43 to 57
00:18:00
I'll share the book and the lecture
00:18:01
links in the description or you can find
00:18:03
it under # DFT on Discord coming to my
00:18:06
personal favorite backend you mainly
00:18:08
have synthesis physical design and
00:18:10
physical verification here prepare for
00:18:13
back end in general so from synthesis to
00:18:15
PD we'll see what all to study in depth
00:18:18
but before we start knowing what not to
00:18:20
study is also important huge respect to
00:18:23
all the nptl courses out there but
00:18:25
physical design by Indra Neil s Gupta
00:18:27
for PD is to totally outdated I can
00:18:30
confirm this by being in the industry
00:18:32
doing practical things though the series
00:18:34
is great for low power designs and DFT
00:18:37
Concepts but definitely not for PD so
00:18:40
then what to study first properly finish
00:18:42
cosos Concepts you can do it from
00:18:44
digital IC design by Jan Raman for
00:18:46
backend you need to complete all these
00:18:48
lectures mainly look out for voltage
00:18:51
transfer characteristics noise margin
00:18:53
leakage short circuit and dynamic power
00:18:55
short Channel effects and logical
00:18:58
efforts logical efforts for PD is very
00:19:00
important you need to know how you can
00:19:03
improve Tran of a circuit by adding a
00:19:04
buffer upsizing pros and cons so watch
00:19:07
this entire lecture series then start
00:19:10
stda for PD sta is very very important
00:19:13
topic make sure you go through all the
00:19:15
concepts properly positive skew negative
00:19:18
skew clock uncertainty false path
00:19:20
multicycle and half cycle paths finally
00:19:22
cover the whole sic backend flow floor
00:19:25
planning guidelines where and how to
00:19:27
place the macros place bement read
00:19:29
everything in this stage from high fan
00:19:31
out net synthesis to logical
00:19:33
restructuring this is an optimization
00:19:35
state so know everything in this stage
00:19:37
CTS clock tree synthesis oh my God this
00:19:40
is every interviewer's favorite topic to
00:19:42
ask questions from so of course Master
00:19:44
it and also this should be your favorite
00:19:46
topic different clock structures why
00:19:49
balancing clock is very important why
00:19:51
you should not have high latencies and
00:19:53
impact on power I'll make a proper
00:19:56
dedicated video for physical design
00:19:57
covering all of this in depth for
00:20:00
references you can refer to vsi backend
00:20:02
Adventure most of the time this page is
00:20:04
down whenever it's up download all the
00:20:06
pages and keep it physical design for
00:20:09
you physical design by Kavita Sharma it
00:20:12
is also a great blog okay so finally
00:20:14
coming to the most interesting part
00:20:16
projects see projects play a major role
00:20:19
in getting you into a company as a
00:20:20
fresher having good projects on your
00:20:22
resume can give you a great Edge also
00:20:25
your project should be aligned to the
00:20:26
job role you're applying to but you
00:20:28
should have one project where you
00:20:30
implement the complete vlsi like say
00:20:32
designing a simple Hardware in very log
00:20:35
writing a test bench and then testing it
00:20:37
and then synthesizing the verified RTL
00:20:39
code and implementing it till it's lay
00:20:42
you can also choose bottom up approach
00:20:43
like first designing the layout of the
00:20:46
gate and then building the hardware
00:20:47
using the gate for front end you can
00:20:49
have design and verification related
00:20:51
projects in very log or system very for
00:20:53
back end you can have a RTL to GDs
00:20:55
implementation which includes doing
00:20:58
synthesis and PNR which is placement and
00:21:00
Route you can also find # projects on
00:21:03
Discord which has complete list of
00:21:04
project lists levelwise for each domain
00:21:07
you can find all the open source tools
00:21:09
also in the PDF don't worry I'll make a
00:21:11
dedicated video for projects for now
00:21:14
start with the projects given in the
00:21:15
project list also you can collaborate
00:21:17
with other students and make projects on
00:21:19
Discord each project is posted levelwise
00:21:21
here okay guys by watching this video
00:21:24
till here you are 50% there and once you
00:21:27
finish off those 10 topics and make up a
00:21:29
strong base no one can stop you tell me
00:21:32
in the comments below if this video
00:21:33
helped you in any way you can also
00:21:35
follow chip cam on Instagram I think we
00:21:37
have made a great Electronics Community
00:21:39
I'll keep getting such videos stay tuned
00:21:42
and see you in the next one
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